Asynchronous data transmissions generally include the transmission of 8-bit characters preceded by a start bit and followed by a stop bit. Conversely to synchronous data transmissions, the receiver does not receive the clock signal from the transmitter so that the respective clocks of the transmitter and of the receiver should exhibit in relation to one another a deviation not exceeding a certain value for the data to be transmitted correctly.
To increase the possibilities of asynchronous data transfer between devices exhibiting clock circuits that are not very accurate and are likely to show large deviations with time and temperature, data transmission protocols have been recently developed to enable a receiver to time its clock signal in relation to that of a transmitter by sending a synchronization character to the latter. Such protocols are consequently less demanding with regards to the deviation of the clock signal of the receiver in relation to that of the transmitter.
The phrase “local clock signal” shall designate the clock signal of the receiver, and “reference clock signal” shall designate the clock signal of the device that transmits a synchronization character. For clarification purposes, FIG. 1 represents the format of an asynchronous frame according to the protocol LIN (Local Interconnect Network) which is available on the web site www.lin-subbus.org. This frame comprises a break character BRK (stop character) comprising a set number of bits equal to 0 and a last bit equal to 1 (extra bit), a synchronization character SYNC, and data characters CH1, CH2 . . . CHN. The character CH1 serves as an identification field to enable multipoint links between a master device and slave devices.
The character SYNC is represented in more detail in FIG. 2 and is equal to [55]h in hexadecimal notation, i.e., the character 10101010 in binary (bits B0 to B7). This synchronization character is preceded by a start bit STB equal to 0 and followed by a stop bit equal to 1. In total, 5 falling edges are available to tune a local clock signal in relation to the reference clock signal of the character SYNC. The time between the 5 falling edges is equal to 8 times the period T of the reference clock signal. Measuring this duration enables one to derive the reference period T and to tune the local clock signal to the latter.
FIG. 3 represents schematically the architecture of a circuit UART enabling one to time a local clock signal CK with the clock signal of a SYNC character. The local clock signal CK is delivered by a divider DIV1, generally a divider by 16, receiving at an input a sampling signal CKS. The signal CKS is delivered by a programmable divider DIV2 receiving at an input a primary clock signal CK0. The ratio between the frequency of the signal CK0 and that of the signal CKS is determined by a value DVAL loaded in a register DREG of the programmable divider.
The circuit UART comprises a buffer circuit BUFC and a status machine SM which identifies the break and synchronization characters, and delivers information signals IS to the outside world. The outside world is, for instance, a microcontroller architecture (not represented) within which the circuit UART has been implanted. The signals IS indicate, for instance, that a character SYNC is being received, and that data received is available for writing into the circuit BUFC, etc.
The buffer circuit BUFC comprises two reception registers SREG1 and SREG2, a transmission register SREG3, a 4-bit counter CT1 (counter by 16), two logic comparators CP1 and CP2, and a circuit AVCC. The register SREG1 is a 10-bit shift register whose input SHIFT is synchronized by the signal CKS. The register SREG1 receives data RDT on a serial input SIN connected to a data reception terminal RPD, and delivers on a parallel output POUT sampled data SRDT (bits b0 to b9). The data SRDT is applied to the input of the circuit AVCC whose output delivers a bit Bi which is sent to a serial input SIN of the register SREG2. Each bit Bi delivered by the circuit AVCC is conventionally equal to the majority value of samples of ranks 7, 8 and 9 (bits b7 to b9) present in the register SREG1.
The data SRDT is also applied to an input of the comparator CPl whose other input receives a reference number 1110000000 forming criteria for detecting a falling edge. The comparator CP1 delivers a signal FEDET which is communicated to the outside world and is also applied to a reset-to-6 input (input SET6) of the counter CT1, which is clocked by the signal CKS. The counter CT1 delivers a signal SCOUNT for counting samples which are applied to an input of the comparator CP2, whose other input receives in binary form a reference number equal to 9 in base 10. The output from the comparator CP2 drives the shift input SHIFT of the register SREG2. Finally, the register SREG3 is a shift register clocked by the local clock signal CK, which receives data XDT on a parallel input PIN and delivers serial data XDT on an output SOUT connected to a terminal XPD
Detection by the UART circuit of the falling edges of a character SYNC is illustrated in FIGS. 4A to 4E, which represent respectively the data RDT, the sampling signal CKS, the signal SCOUNT, the data SRDT sampled by the register SREG1, and the signal FEDET. When the signal FEDET becomes a 1, this indicates that a falling edge is detected, and occurs when the data SRDT is equal to 1110000000. The falling edges are detected after reception of seven samples equal to 0. The counter CT1 is tuned back to the value 6 (i.e., the seventh counting cycle from 0) when the signal FEDET becomes a 1.
After reception of the character SYNC, the data present in the characters CH1, CH2 . . . is received one bit at a time. A data bit Bi is delivered by the circuit AVCC (majority value of the samples b7 to b9) which is loaded in the register SREG2 every 16 cycles of the signal CKS, i.e., at each cycle of the local clock signal CK. A bit Bi is loaded at the tenth counting cycle of the counter CT1 when the output from the comparator CP2 becomes a 1. The data received RDT is stored in the register SREG2 by a group of 8 bits B0-B7 and can be read by a parallel output POUT of that register.
The character SYNC represented in FIG. 2 enables an external calculation unit, for instance the central unit of a microcontroller, to determine the value DVAL to load in the divider DIV2 to compensate for a deviation of the local clock in relation to the reference clock. This value is such that the period Ts of the sampling signal CKS must be equal to:Ts=D/(8*16)D is the time measurement between the five falling edges of the synchronization character, i.e., eight periods T of the reference clock. DVAL can be calculated by software, or by a specific circuit with wired logic which can be associated with the status machine SM.
In spite of the advantages of re-synchronization of the clock due to the character SYNC, there is still a large deviation of the local clock which jeopardizes good reception of asynchronous frames. This is the case when the deviation of the local clock in relation to the reference clock is greater than the set tolerance margin. This tolerance margin depends on the number of bits equal to 0 of the break character BRK preceding the character SYNC.
Within the framework of the protocol LIN, this tolerance margin is ±15% since a break character comprises 13 bits equal to 0, and it is considered that a 11-bit detection at 0 is sufficient to detect the break character. Beyond this tolerance margin, reception of the character break can be inaccurate. For instance, a receiver having a local clock exhibiting a deviation greater than ±15% may believe that it is receiving a break character, whereas the character received is another character or is formed by a sequence of other characters. In such a case, clock retiring based upon the SYNC character may prove useless since the very detection of the bits of the character SYNC is uncertain. Thus, there is a need to address this shortcoming.